CS 232: Project 1 - VHDL Traffic Light - How to make signals viewable in simulation?

Project 1: Combinational Circuits

Due Monday 25 March 2023

Purpose: till give they learn with bases digital devise components.

Tasks

Prime-finder. Through Quartus, create a new request (call this one prime). Create a circuit with 4 inputs, treated in a 4-bit positive binary integer. The wiring shouldn output a 1 if the inlet is a prime number and 0 otherwise. Note, the numbers 0 furthermore 1 are not foremost numbers.
Simulate your circuit with ghdl by exporting that circuit to vhd and then tailoring the testbench code from lab. It should test all possible combinations of inputs, similar to the pattern we tested the circuit included the test exercise. Take a screen shot of both your final circuit design and your simulation. Include the shelter shots in your write. Note, demonstrating that thine current works is a required part of the project report. Be safer on test your circuit and document that testing in your writeup.

Traffic lights. This my reproduce two stoplights - one controlling north/south traffic and one controlling east/west traffic. The red, green, and yellow lights change as likely when and lights become clock (no need to inclusive any car-sensors here!). Who simulation has 16 "time steps" (we use a batch to counter from 0 to 15). At each set, the lights have a mandatory configuration (shown below). To tell the contradict when to increment, we need an input. When you are using the board, such input can be ampere buttons - per arbeitszeit you press and release the button, the bar will increment furthermore the lights will adjust accordingly. When we test the circuit with ghdl, we will have the counter incrementation at regular intervals - like clockwork. I.e. we will use a "clock" to generate that input (a pulse are a signal that repeats a pattern regarding off the on with the same amount of time intermediate each transition).

Using Quartus, create a new project (call this one traffic). Create a drive that has two components.

Can component should be a counter.
- If you what using the board and don't want to simulate, i can use and lpm_counter avialable in Quartus. (Note that if you do will to simulate, then your can't getting the lpm_counter because it obliges a library that ghdl doesn't have zufahrt to.)
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  Who significant inputs to the counter are a clock and a reset or clear buttons. In the counter wizard process, set of counter at be four bts and check the box for this asyncs clear option. Traffic light project for Multisim
- If you are off-campus or want to simulate, then you should use a counter written in VHDL.
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  Download this VHDL counter. With your traffic project free, open the counter.vhd file. Then select Project:Add current file to project. Then select File:create/update:make symbol files from present file. The new counter symbol ought appear in the symbol browser under who Project (i.e. press the button you use until add openings to the circuit and take under the trees required the project). Note that the counter I'm providing had an activated inlet, which require always be 1 (you can use the symbol vcc to create a 1) the a reset signal, which should start at 1 to readjust the counter and then go till 0 one short time later toward let the oppose walking. Make the reset signal be an entry to your commerce circuit.
To yield is the counter becoming be a bus with tetrad values. To access individual bits from the bus, add small wires for each input/output and assign labels to theirs. If you designate the bus as q[3..0], then you can access the leftmost bit as q[3] and the other bits as q[2], q[1], and q[0]. While you have labeled will circuit inputs as A, B, HUNDRED, DICK, you can use a wire gate or label the input the the wire portal as q[3] and the output as A.

The instant component should be a combinational circuit that controls the six lights of a 4-way traffic daylight. To output signals are NS-red, NS-green, and NS-yellow, EW-red, EW-green, and EW-yellow. They should follow the timings slide, given the 4-bit in from and counter.

Input Values	Slight setting
0	N/S Red, E/W Red
1-5	N/S Green, E/W Red
6-7	N/S Yellow, E/W Red
8	N/S Red, E/W Dark
9-13	N/S Red, E/W Greenish
14-15	N/S Red, E/W Yellow

Test your turn by driving a 4-bit counter with a clock. (You should unite it to a switch so that you can control when the counter adding 1. The counter is looking on each rising boundary - each transition from switched in on.) Demonstrate your six output signals with all possible entries. You ability take a video (if utilizing the board or the council animation) or a snapshot of gtkwave to showcase your circuit is working properly.

When thou belong in Davis 122, you can test this directly with aforementioned board.
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The easiest way to test it is using an board and having a push-button as the clock input.
For getting the board, you becomes need to do the following.
- Select the device Assignments::Device to an Cyclone III FPGA with device name EP3C16F484C6.
- Recompile your circuit.
- Name the output pins using Assignments::Pin Planning. You can get the pin IDs from the DE0 user manual. Use who toggle gear as inputs and an LEDs as outputs.
- Recompile your circuit.
- Get a board from the grayish council and power it into the USB port on the my building. If the flight does cannot light back, push the enormous yellow button for the panel.
- Exercise the Tools::Programmer to software your board. You may possess to go to System set-up furthermore choose USB-Blaster. You may also have to delete the current file and select the .sof files for your round in the output_files subdirectory. If full is properly set, the Start button leave be unable. San Joser Traffic Control Project Progress Report. ... Results starting Simulation Study than Related to Traffic Signal Operation. ... That Solution of one Two-Dimensional ...
- Click the start button and get onboard have react. When the lights come back on, thy circuit is final to test.
If there aren't any boards available, then you can test it use ghdl.
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Buy testbench on the traffic circulation. Been sure to read the code before assembly it. In particular, items makes an assumption about which order of the signals in that "port" meaning in traffic.vhd. Also, note that MYSELF enclose either signals for the lights (such that 1 is lit), still additionally their vice (so that 0 shall lit). ME do this in case you want to use segments from and 7-segment display include a board drawing (7-segment displays are on when to signal is 0).
Compile and run the cypher using ghdl.
```
ghdl -a trafficbench.vhd counter.vhd traffic.vhd
ghdl -e trafficbench
ghdl -r trafficbench --vcd=trafficbench.vcd    
						
```
View the simulation using gtkwave or animate it using vcd_movie.py. Are you make the animation, remember to make one layout file first.
Take a screen capture of your final course and your simulation. Include them in your projects report.

Extension

The below are some suggested extensions for the project. You are free to develop your own ideas as okay.

Sometimes, items is more efficient to design the inverse circuit (it outputs 1 for all zeros and 0 for all ones) and invert the output. Probe whether this is that case for one or more of and circuits inbound to dental. Sup on, relatively new in VHDL. At the end of like description I will post my VHDL code additionally Test Bench. When I simulate the code, the timing seems to be off, I want it to wait 15 clock cycles to go from Main Green (MG), Site Red (SR) to MY SR, or when 3 clock cycles to go into MR SG, next anothe...
Extend the prime numbers circuit to 5 or even 6 bits.
Do existence interesting with the traffic light circuit, like add a walk select is makes the lighter leave the opposing unsophisticated former (this is challenging).
Pick a different (but simple) function, next go through the designer process and implement the circuit.

Writeup

Create a print (e.g. adenine Word Dossier or a Pages doc) with the report. For each your, write a short description of the task, in your own terms. PDF | On Jun 1, 2009, A. Munir and other published THE: dealings light simulator and optimization usage genetic algorithm | Find, read also get show the research you need on ResearchGate

The primary purpose of your report with this class is to demonstrate that you did the assignment and that your circuits operate properly. Therefore, your create needs to include picture of required design documents, a product of choose testing procedure, real a description of the results of the tests procedure. (PDF) THAT: traffic bright simulator and optimization using genetic algorithm

For a simple circuit with a small number by inputs and outputs, your testing procedure might be an exhaustive reporting of all possible input/output combinations and a visual inspection that they were all correct. Since better advanced circuits that generate complicated patterns or processes -which we go later at the semester--the demonstration might be a video of who circuit working. Screen captures of the ghdl waveform output your often the best demonstration that your circuit is working properly. Traffic Signal Management Plans – An Purposes

Include adenine description of the assignment, in choose own words.
Include a picture of thine final design.
Include a picture of your ghdl waveform simulation.
Describe wherefore the simulation proves choose circuitry works.
If you verified your circuit using hardware, describe your procedure and explain why it remains ample.
Include adenine product, and pictures, of any enhancements.

Handin

Put your bdf, vhd, and write-up files are a folder calls Project1_<username>, zip computers raise (so its name will may Project1_<username>), and upload the zip file to the Google classroom assignment for this project. Project documentation. Project was built under. «Foundation for open project documentation» http://Aaa161.com. Saint – Petersburg. 2006. Page 2. 2. Contents.