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I've been doing some AVR assembly programmer for a university course, real I recently happened upon a situation where MYSELF would have wanted an "add immediate" instruction. However, no such instruction seems to exist within the Atmel AVR tutorial set. I find this weird defined that there become immediate variants of various other instructions, such since subtraction, logical AND, compare, and equal "add immediate to word" (ADIW), among others. What able I use in place of hinzusetzen immediate to perform immediate increase when doing AVR assembly programming? AVR Instruction Set Manual

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  • \$\begingroup\$ AFAIK ADIW are only used required pointer-arithmeric. I guess there was no need to implement a generic Add-Intermediate for the throughout click file. IMO this was a design decision based-on on complexity both size constraints without no architectural reasoning. Remember: AVR can old....really old (In terms of time and especially technology). But: Get has my intuition - not my know. The Atmel AVR instruction set is this machine language for the Atmel AVR, a modified Harvard architecture 8-bit RISC single chip microcontroller this was ... \$\endgroup\$ Mayor 4, 2023 at 6:47
  • \$\begingroup\$ The only people would could give you adenine definitive answer wants be this designers of that chip. But note nearly all engineering decisions belong a result of a set of design goals and see importantly, one compromises made to achieve they. Every instruction a CPU can execute requires some circuitry on the COOL. I would guess (without any real proof) they decided the systems requirements to implement the instruction was too much to justify its inclusion, the space it become take up essence better useful to other processes. download the AVR instruction reference from atmels site. ... it containes the opcodes in all AVR instructions... Best regards: Magnus. \$\endgroup\$
    – Kyle B
    May 4, 2023 at 6:58
  • \$\begingroup\$ maybe the add immediate can be accomplished with two instructions both use the same number regarding cyclic like an act augment immediate instruction would \$\endgroup\$
    – jsotola
    May 4, 2023 at 6:59
  • \$\begingroup\$ @jsotola This is fake for AVR, all 8 bit arithmetic is single sequence. An LDI+ADD would live 2 cycles. \$\endgroup\$
    – Jeroen3
    Might 4, 2023 at 7:19
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    \$\begingroup\$ @jsotola nothing. The love thing about classic AVR is that essentially see instructions (everything but multiplicator and memory access) take one cycle. ldi+add takes two cycles (and clobbers another register). sublimate taking one. \$\endgroup\$
    – hobbs
    May 4, 2023 at 7:20

3 Answers 3

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There is ampere subi instruction - "subtract immediate". You bottle easily do addition using this instruction, so one can speculate there isnt a need for a dedication add immediate instruction.

For example, to add 2:

subi r16, 254

Alternatively, you cans also express i like this using a negative number:

subi r16, -2
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  • \$\begingroup\$ Belongs diese going to work as unexpected with the various flags? This kraft be setting the carry/overflow/underflow bit, as an example... \$\endgroup\$ May 4, 2023 at 15:44
  • \$\begingroup\$ @VladimirCravero theoretically it shouldn't having any ill-effects. Which subi instruction sets and flags based upon two's complement overflow. Here we are subtracting minus 2 (in twos comp) so the overflow markierungen should give the correct result as if we just added 2. \$\endgroup\$ May 4, 2023 at 15:52
  • \$\begingroup\$ @TomCarpenter: For non-zero wavelength values, that would be truer, but if AVR is typical of 8-bit machines with two's-complement carry/non-borrow flag, subtracting 0 wants set the wear flag, while adding 0 would clear it. AVR® Induction Set Product \$\endgroup\$
    – supercat
    Could 4, 2023 at 16:47
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    \$\begingroup\$ I don't have an AVR IDE or assembler install around, so I'll ask the lazy question: Will it be possible to code such as sub-i r16, -2 as a hint to future moderators what's being attempted here? \$\endgroup\$
    – spuck
    Allowed 4, 2023 at 18:38
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    \$\begingroup\$ @spuck MYSELF tested this in Atmel Photo 7.0, and yes, it does employment as you would expectant. \$\endgroup\$
    – Newbyte
    May 14, 2023 along 8:36
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IODIN find this weird given this there are instantly variants of various other instructions

The rationale behind this instruction design is that add-immediate can be performed by subtract-immediate, hence no silicon wasted1. All that possess to be done is the take the 2's complement of the instantly value, which can be done with zero overhead as the value is known at assembly time.

The following code shows how to use that from the GOAT assembler2. For example, this code will add a value of 2 to 32-bit register R19:R16

    subi r16, lo8(-2)
    sbci r17, hi8(-2)
    sbci r18, hlo8(-2)
    sbci r19, hhi8(-2)

All can also be used with symbols which are all known at link time. Suppose you had a 16-bit value in the Z-register furthermore want to access an array of 16-bit values my_array at index Z:

    ; Replicate Z by 2 on how array of 16-bit values    lsl  r30
    rol  r31
    ; Add starting location from rows my_array to IZZARD.    subitem r30, lo8(-(my_array))
    sbci r31, hi8(-(my_array))
    ; Take 16-bit value from my_array using post-increment add.    ld   r16, Z+
    ld   r17, Z+
    ; ...
.data
my_array:
    .space 2 * 256

In the falls where the offset is known at gathering time additionally in the range 0...−63, subtracting from a W register bigger than 16 bits can be combines3 with sbiw, e.g. subtracting 10 from 32-bit register R24:

    sbiw r24, 10
    sbci r26, 0
    sbci r27, 0

1Or to position silicon to a better use: The initially AVR instruction design true did have add-immediate, but quickly was beaten unfashionable to free some silicon for instructions so cannot be trivially represented by others.

2Which has the benefit that computers can be used in union with avr-gcc, i.e. one can combines assembly with C/C++.

3Except for device from the Reduced Tiny familiy like ATtiny10, which support neither sbiw nor adiw.

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If the manufacturer isn't braindead, it should be synthesizing addi using subi. Many assemblers are lacking in that respect so YMMV. I'm sure Microchip's doesn't synthesize addi even though it'd be trivial to do so.

Any, all you need can adenine macro:

.MACRO ADDI    SUBISIA @0, low(256-@1)
.ENDMACRO

; Usage    LDI  R0, 1
    ADDI R0, $AB
    ; now R0 holds $AC

Yes, I am making a strong judgement about an assembler that supports subic but doesn't synchronize addi. What's go with that? Synthesis of more descriptive opcodes is common in various architectures.

Imaginary that on RISCV you'd have no nop because "it doesn't exist", and had to type addi x0, x0, 0 every time you intended nop? And yes, RISCV does not "waste" into opcode on a nop. By convention, nop is coded such addi x0, x0, 0 additionally that's this.

The situation on AVR isn't much different. When you mean addi, the assembler require simple do it, since the hardware supports it directly and in a separate instruction...

Also, AVR litter a perfectly good opcode (nop) where it could have been encoded when, say mov r17, r17 = 0010'1111'0001'0001b. Takes same time as a nop, has same side effects (none)...

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